Packaging technology for integrated circuit (IC) structures has been continuously developed to meet the demand toward miniaturization and mounting reliability. Recently, as the miniaturization and high functionality of electric and electronic products are required, various techniques have been disclosed in the art. To increase the density of package structures, multiple dies may need to be packaged in a same package structure. To accommodate multiple semiconductor dies, an interposer is typically used to bond integrated circuit dies thereon, and the resulting structure including the interposer and the semiconductor dies are treated as a single structure.
Package technology may involve stacking multiple semiconductor dies to achieve a high level of integration in semiconductor devices. Thus, through silicon vias (hereinafter abbreviated as TSV) and interposers are used to provide electrical connections for the stacked semiconductor dies. By involving those approaches, the spacing distance between semiconductor dies is reduced and the size of the semiconductor package is shrunk while electrical performance and operation frequency of the semiconductor package are both improved.
This “Discussion of the Background” section is provided for background information only. The statements in this “Discussion of the Background” are not an admission that the subject matter disclosed in this “Discussion of the Background” section constitutes prior art to the present disclosure, and no part of this “Discussion of the Background” section may be used as an admission that any part of this application, including this “Discussion of the Background” section, constitutes prior art to the present disclosure.